Peripheral Component Interconnect Express (PCIe) is a computer serial bus expansion standard that replaced the older PCI standard and similar technologies. A PCIe bus is designed to enable a processor to communicate with peripheral components that are attached to a computer system such as disk drives, storage devices, networking interface cards and similar components. The PCIe specification defines layered architecture that enables multi-gigabit per second serial interface communication between the components of the computer system communicating over the PCIe bus.
In a standard computer system it was expected that a central processing unit or similar processing device would control the PCIe bus via a root complex. The root complex connects the processor and memory subsystems to the PCIe bus, which may be considered a switch fabric composed of any number of switch devices. The root complex generates transaction requests on behalf of the processor. In the basic PCIe architecture the processor and its root complex perform a discovery process during start-up of the system. The discovery process determines what devices or components are connected with the PCIe bus. The discovery process maps these devices into the memory space of the processor. This is generally achieved through transparent bridging where the processor discovers all endpoint in its address domain.
Non-transparent bridge (NTB) is an alternative to transparent bridging where the bridge connects two devices with separate address spaces. The two devices using non-transparent bridging have independent address spaces and considers the other device as an endpoint. The two devices map the other address space to their own address spaces to enable communication. Where NTB is utilized in conjunction with a PCIe bus, the PCIe bus must perform address translation between the two address spaces.
PCIe busses have been utilized in network devices, which were not the original target environment. Such network devices include routers and switches. However, network devices present difficulties for the operation of a PCIe bus where in a network device multiple processing devices and root complexes may be present that communicate with one another over the PCIe bus and with connected components.